As with any processor vendor, having a detailed list of what the processor does and how to optimize for it is important. Helping programmers also plan for what’s coming is also vital. To that end, we often get glimpses of what is coming in future products by keeping track of these updates. Not only does it give detail on the new instructions, but it often verifies code names for products that haven’t ‘officially’ been recognized. Intel’s latest update to its ISA Extensions Reference manual does just this, confirming Alder Lake as a future product, and identifies what new instructions are coming in future platforms. Perhaps the biggest news of this is actually the continuation of BFLOAT16 support, originally supposed to be Cooper Lake only (and bearing in mind, Cooper Lake will have a limited launch), but will now also be included in the upcoming Sapphire Rapids generation, set for deployment in the Aurora supercomputer in late 2021.

In the 38th Edition of the ISA Extensions Reference manual from Intel, the company has a table front and center with all the latest updates an instructions coming to future platforms. From this, we can plot what platforms will be getting which instructions.

Intel Instruction Support
AnandTech Tremont
Atom
CPR
Xeon
ICL
Xeon
SPR
Xeon
Tiger
Lake
Alder
Lake
PCONFIG     ?    
WBNOINVD     ?    
Intel MKTME     ?    
ENCLV   ?    
MOVDIR*     ?
AVX512_BF16   no    
AVX512_VP2INTERSECT       ?
CET       ?
ENQCMD*          
PTWRITE          
TPAUSE, UM*        
Arch LBRs        
HLAT        
SERIALIZE        
TSXLDTRK          

Starting with what I think is big news: BF16 support in Sapphire Rapids. It is clear from this manual that BF16 will not be supported in Ice Lake Server, which means that technically BF16 will skip a generation, going from Cooper Lake to Sapphire Rapids. But as we’ve reported on previously, Cooper Lake has changed from a wide launch for everyone to a minimal launch for select customers only, and those that focus on 4S and 8S topologies (like Facebook). So this could be considered more of a ‘delayed’ launch, assuming Sapphire Rapids is going to be widely used. Anyone planning to use Cooper Lake for BF16 compatible workloads will have to wait an extra couple of years.

The other big news is the mentioning of Alder Lake. Up until this point, Alder Lake has only been mentioned in unconfirmed slides, or LinkedIn profiles of engineers who have worked on it (and subsequently those references were removed). As far as we understand, Alder Lake is the 10nm product following on from Tiger Lake. Tiger Lake (what we know so far) is a quad-core mobile chip due for launch at the end of 2020, which means Alder Lake is likely to be at the tail end of 2021.

What Alder Lake (and Sapphire Rapids) gets for instructions includes Architectural LBRs (Last Branch Recording) in order to speed up branches, HLAT (Hypervisor-managed Linear Address Translation), which forces linear address translation, and SERIALIZE, which forces a command to go through a core with all the caches pre-flushed and waits for all buffered writes to have finished before starting.  The LBR update helps with performance, the HLAT is primarily for Sapphire Rapids, and the SERIALIZE is to assist with recent security issues.

Also of note are some of the Ice Lake Server updates. It now lists Ice Lake Server as getting Intel’s MKTME, Intel’s Multi-Key Total Memory Encryption, which are a set of memory encryption techniques for multiple encrypted environments, increasing the scope of these technologies with a key to matching/surpassing AMD’s prowess in this area. The other one to note (but not new for this document) is ENCLV support, which SGX related to secure enclaves.

Another point of security is the new TSXLDTRK instruction for Sapphire Rapids. This is a TSX Load Tracking ‘suspend’ instruction, with a corresponding XRESLDTRK to resume load tracking for TSX. (TSX = Transactional Memory.)

The full information about these new instructions can be found on Intel’s Developer Zone.

Source: Instlatx64 on Twitter

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  • Deicidium369 - Tuesday, April 28, 2020 - link

    Interesting in that they will be used with Intel Xe, Intel Agilex (FPGA) and the Habana AI stuff - and programmed under One API. They are all gunning for CXL which is transported over PCIe5 - which is already in Agilex and will be in Sapphire Rapids. Reply
  • Duncan Macdonald - Wednesday, April 1, 2020 - link

    The problem for Intel is if they removed all the shortcuts then the performance would suffer - quite possibly to the point where even the fastest Intel CPUs were slower than AMD's CPUs.
    Intel already has the problem that its current monolithic architecture can not match the number of CPU cores per package that AMD can get with its chiplet design (eg in the EPYC 7742). If Intel moved from its current monolithic design to a chiplet design like AMD and fixed the security busting shortcuts then it might well have difficulty matching the performance of the current AMD Zen 2 devices at the time that AMD Zen 3 is on the market.
    Reply
  • yeeeeman - Wednesday, April 1, 2020 - link

    Why it would have problems matching the performance of Zen 3? Ice Lake in mobile form factor (so smaller cache size) already has 10% better IPC than Zen 2. Given Zen 3 is rumoured to have 10-15% better IPC than Zen 2, then it would be a tie between Ice Lake core for server and Zen 3.
    The biggest advantage that AMD has IMO is 7nm process, courtesy of TSMC.
    Chiplets wouldn't be such a success with an old process like 14nm from Intel. Efficiency would be crap.
    So all in all, sure, Intel is blamable for its stupid mistakes related to security. But there isn't really much they can do given the process issue still persisting and TSMC going along so well.
    Reply
  • yeeeeman - Wednesday, April 1, 2020 - link

    And again, the Zen 2 core is nothing spectacular on its own, it barely overtakes Skylake in IPC, which is ancient now by technology standards.
    Again, 90% of AMD success is thanks to TSMC, not a real technical superiority that AMD has.
    Reply
  • Qasar - Wednesday, April 1, 2020 - link

    too bad most places, ice lake is no were to be found. " it barely overtakes Skylake in IPC" um yea ok. clock any intel cpu the same as Zen 2, and see what happens, the only reason intel has any performance advantage, is because of clock speed, and it gets that performance, while using more power. Reply
  • name99 - Wednesday, April 1, 2020 - link

    "90% of success is showing up"
    And 90% of business success is knowing what to do in-house, and what to sub-contract out to experts...
    Reply
  • mode_13h - Wednesday, April 1, 2020 - link

    You're forgetting the decade (2005 to 2015, roughly) where Intel basically lead the world in semiconductor manufacturing, by up to a couple years.

    Intel's mistake wasn't failure to subcontract out, but rather its failure to adequately invest in protecting that competitive advantage.
    Reply
  • Kevin G - Wednesday, April 1, 2020 - link

    The problem is that the basic Sky Lake core is essentially what Coffee Lake currently is. Matching IPC means the the performance difference stems mostly from clock speeds which Intel has a clear edge at the high end but due to their product segmentation they’re keeping their midrange and lowend chips handicapped a bit in terms of clocks and cache.

    The other factor is that for those keeping up-to-date on security patches, Intel’s platforms have gotten slower over time because of them. This varies based upon workload as I haven’t felt much of a difference at home but an older box at work did indeed take a 25% performance hit (IO heavy and uses VMs). AMD’s technical superiority here clear and all they had to do was not screw up security as bad (they’re not perfect).
    Reply
  • Jorgp2 - Wednesday, April 1, 2020 - link

    you're wasting your breath.

    These people don't think before they speak
    Reply
  • kaspar737 - Wednesday, April 1, 2020 - link

    Ice Lake 10% better IPC than Zen 2 if security mitigations are disabled? Reply

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