TSMC: Most 7nm Clients Will Transition to 6nm
by Anton Shilov on May 1, 2019 6:30 PM EST- Posted in
- Semiconductors
- TSMC
- 7nm
- 6nm
In this week's quarterly earnings conference call, TSMC’s revealed that the company expects most of its 7nm "N7" process customers to eventually transition to its forthcoming 6nm "N6" manufacturing node. The upcoming node will use the same design rules as the N7 node, making it easier for customers to transition to the newer, denser node. And, if TSMC's predictions come true, N6 is now on the path towards becoming another widely-utilized, long-serving process node for the company.
In comments made during the quarterly call, CC Wei, TSMC's CEO and vice chairman noted that “most of the customers in the N7 will move to N6.” In fact it sounds like TSMC's N6 node is set to become another one of TSMC's popular, high volume nodes, with Wei further stating that “from that day on probably, the N6 will pick up all the momentum and pick up all the volume production.”
As previously reported, TSMC’s N6 process technologies adopts extreme ultraviolet lithography (EUVL) to lower manufacturing complexity by reducing the number of exposures required for multi-patterning (which is needed today as TSMC’s N7 uses solely DUV lithography). While TSMC's N7+ uses up to four EUVL layers, its N6 expands it up to five layers, whereas N5 expands usage of EUVL all the way to 14 layers.
UPDATE: Correcting the number of EUV layers used by N6 and N7.
While TSMC’s N6 uses new production equipment and offers 18% higher transistor density than the company’s N7 manufacturing technology, N6 uses the same design rules as N7 and enables designers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will allow them to lower development costs. By contrast, N7+ uses different design rules, but also provides more advantages than N6 when compared to N7.
| Advertised PPA Improvements of New Process Technologies Data announced by companies during conference calls, press briefings and in press releases |
|||||||||
| TSMC | |||||||||
| 16FF+ vs 20SOC |
10FF vs 16FF+ |
7FF vs 16FF+ |
7FF vs 10FF |
7FF+ vs 7FF |
6FF vs 7FF |
5FF vs 7FF |
|||
| Power | 60% | 40% | 60% | <40% | 10% | ? | 20% | ||
| Performance | 40% | 20% | 30% | ? | same (?) | ? | 15% | ||
| Area Reduction | none | >50% | 70% | >37% | ~17% | ~15% | 45% | ||
While TSMC’s partners have adopted both N7 and N7+ processes and the world’s largest contract maker of chips expects the two technologies to contribute over 25% of its wafer revenue in 2019, the former looks to be somewhat more popular that the latter. Meanwhile, TSMC projects that most of its customers who use N7 today will migrate to N6 and then to N5 skipping the N7+. Considering how widespread N7 is going to get, N6 will likely be quite popular as well.
Related Reading:
- TSMC Reveals 6 nm Process Technology: 7 nm with Higher Transistor Density
- TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready
- TSMC: 7nm Now Biggest Share of Revenue
- TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
- TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains
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Anymoore - Thursday, October 3, 2019 - link
TSMC themselves said only few customers were interested in 7+, expecting only 30 million usd in revenue. What's a little surprising is introduction of N6, after already promoting 5nm or N5, and expecting most to choose 6. It suggests that N5 is less compelling than previously thought.FunBunny2 - Thursday, May 2, 2019 - link
It would be useful to have either a standalone article, or some boiler-plate for articles such as this, which delineates how much new tooling from the likes of ASML is required to make the transition to a 'smaller' node. In this case, is TSMC leveraging proprietary process changes on existing tooling (that all vendors have), or are they beneficiaries of new tooling from the likes of ASML.One way or the other, is their a coming step where all vendors are dependent on ASML/et. al. devising (at least some) new machines?
Speedfriend - Thursday, May 2, 2019 - link
Given ASML is the only player in EUV and all future nodes now depend on EUV, they are 100% dependent on machines from ASML and also the future High NA EUV machines from ASMLMeteor2 - Thursday, May 2, 2019 - link
Which always leaves me wondering how come Intel has made such a mess of their process shrink, while TSMC have smashed it.peevee - Thursday, May 2, 2019 - link
Some kind of talent loss earlier in the decade, or advancement of management from a certain country which has zero successful high-tech companies, or both.Wilco1 - Thursday, May 2, 2019 - link
How well would you do in a Formula-1 race? The cars are fairly similar but who drives it matters. The same is true for processes, the machines are the same, but you need to design a complex recipe to build working chips.TSMC has done so well by taking small steps at a time to reduce the risk when moving to a new technology - for example they based their first FinFET process on the already mature 20nm process. Intel tried "hyperscaling", making several complex changes in one go, which is very risky and didn't work out. As a result TSMC has already started producing chips at twice the density of Intel's 10nm process.
FunBunny2 - Friday, May 3, 2019 - link
"The same is true for processes, the machines are the same, but you need to design a complex recipe to build working chips."given. but the question isn't about process, alone. the question is what, specifically, allows one vendor, TSMC, to produce 'smaller' node than other vendors using the same 'commodity' machinery? does it just boil down to more complex masking? or some other specific steps? and so on. I assume that how these machines work is well known to those in the business, i.e. they ain't many secrets. granted, Xnm stopped meaning the same set of dimensions of the same features years ago.
Wilco1 - Saturday, May 4, 2019 - link
In principle you can get the same maximum density when using the same machines. TSMC 7nm and initial Intel 10nm get around 100 million transistors/mm^2. However while Intel reduced their 10nm density to get it working, TSMC has already moved to the next generation machines using EUV which support 175 mT/mm^2.However it's worth understanding there is a huge amount of design just to get a working transistor. It takes around 75 masks and hundreds of steps during 3-4 months using exotic metals and corrosive chemicals to create transistors and wire them up. Any minor issue can destroy many millions worth of chips. That includes chemicals which aren't pure enough as TSMC found out.
drexnx - Thursday, May 2, 2019 - link
bet too much on novel new metals (Ruthenium and Cobalt) to reduce parasitic capacitance, and quad patterning in lieu of EUV and it sounds like neither bet paid off.